Low jitter PLL of high multiplication ratio (1)

Low jitter PLL of high multiplication ratio technology architecture

Low jitter PLL of high multiplication ratio technology architecture


[Features]
Excellent input jitter control by hybrid method.


(Notice)
 This R&D technology was supported by "Shikoku Bureau of Economic,
 Trade & Industry Department", as "Business realization support program
at the venture company R&D challenge" in FY2006.